Integrated circuits should be tested following manufacture to ensure their proper operation. Design-for-Test is a design technique that adds testability features to the design of integrated circuits to improve the application of manufacturing tests. For this reason, integrated circuits are typically provided with a test access port (TAP) that conforms to Institute of Electrical and Electronics Engineers, Inc., (IEEE) 1149.1, or Joint Test Access Group (JTAG), standard. JTAG specifies a “boundary scanning” technique in which automated test equipment (ATE) connected to the TAP via a JTAG (serial) bus provides a clock signal and one or more patterns of zeroes and ones (a “test pattern”) to the integrated circuit and receives a resulting (“output”) pattern of responses by the integrated circuit to the test pattern. An output pattern that does not match expectations indicates a failed test. The ATE may analyze the output pattern to determine the nature of the integrated circuit failure and perhaps where in the integrated circuit the failure occurred. Additionally, the ATE may provide signals to direct the testing and operation of the integrated circuit including a scan enable signal.
A tool, such as an Automatic Test Pattern Generation (ATPG) tool, may be used to generate the test patterns. An ATPG tool is used to find a test pattern that, when applied to the integrated circuit, allows a tester to determine between correct circuit behavior and faulty circuit behavior caused by defects. The test patterns generated by the ATPG tool include zeroes and ones (i.e., bits) that are designated as care bits and don't care bits. For example, a test pattern such as X1XXX0 includes two care bits (1 and 0) and four don't care bits as represented by the four “X”s. The logic value of care bits are important since they are used to provide a fault pattern or perform a function for the testing. On the other hand, the logic value of the don't care bits is not critical for testing.
Test patterns can be shifted into scan chains of the integrated circuit as driven by a scan clock signal provided by, for example, an ATE. The scan clock signal can then be stopped and the output patterns can be captured in the scan chains during application of clock pulses (i.e., a capture clock signals). The captured output patterns can then be shifted out of the scan chains as driven by the scan clock signal that is reapplied. The captured output patterns may be provided to the ATE for analysis. A scan chain is a connection of flip-flops in an integrated circuit that can be configured as a shift register and used to receive test patterns to test an integrated circuit. Scan chains may be connected to the ATE via the TAP interface. A clock gate may be used to control application of the scan clock signal and the capture clock signal to certain scan chains of an integrated circuit. Clock gates and clock gating may be used in integrated circuits to control power when the integrated circuits are in the functional mode and, thereby, provide the opportunity to reduce power consumption.